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4.4 Area Select Register (ASR) and Area Mask Register (AMR)
The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify the
range of address space for chip select areas 1 to 5.
ASR1 to ASR5 specify the upper 16 bits (A31 to A16) of each address, and AMR1 to AMR5
mask the corresponding address bits. Each bit of AMR1 to AMR5 assumes "care" by "0" and
"don’t care" by "1".
When the value set in the ASR is "0", "care" indicates the address space as "0". When it is "1",
"care" indicates the address space as "1".
"Don’t care" indicates the address space for both "0" and "1", that is, irrespective of the value
set in the ASR.
The following is an example of specifying each chip select area by combination of the ASR and
AMR:
(Example 1)
are set, the AMR1 bits corresponding to the ASR bits that are set to "1" are "0", and the address
space of area 1 becomes 64 kilobytes, as shown below.
(Example 2)
are set, the ASR2 bits corresponding to the AMR2 bits that are set to "0" are "1" and "0" to
indicate "care", while the ASR2 bits corresponding to the AMR2 bits that are set to "1" are "0" or
"1" to indicate "don’t care". Therefore, the address space of area 2 becomes 256 kilobytes, as
shown below.
The address space of each of areas 1 to 5 can be optionally located in at least 64 kilobytes in a
4 gigabyte space, using ASR1 to ASR5 and AMR1 to AMR5. When the area specified by these
registers is accessed via the bus, the corresponding chip select pins (CS0X to CS5X) are
handled as L outputs.
Area 0 is allocated to a space other than the areas specified by ASR1 to ASR5 and AMR1 to
AMR5. When these registers are reset, an area other than 00010000
H
and 0005FFFF
H
is
allocated by the initial values of ASR1 to ASR5 and AMR1 to AMR5.
<Note>
Set chip select areas such that overlapping does not occur.
When ASR1 = 00000000 00000011
B
and AMR1 = 00000000 00000000
B
00000000 00000011 00000000 00000000
B
(00030000
H
)
to
00000000 00000011 11111111 11111111
B
(0003FFFF
H
)
When ASR2 = 00001111 11111111
B
and AMR2 = 00000000 00000011
B
00001111 11111100 00000000 00000000
B
(0FFC0000
H
)
to
00001111 11111111 11111111 11111111
B
(0FFFFFFF
H
)