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APPENDIX B Interrupt Vectors
APPENDIX B Interrupt Vectors
Table B.1 and Table B.2 list the interrupt vectors.
The interrupt vector tables list causes for MB91F109 interrupts together with interrupt
vector or interrupt control register assignments.
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Interrupt Vectors
Table B-1 Interrupt Vectors (1/2)
Cause for the interrupt
Interrupt No.
Interrupt
level *1
Offset
TBR default
address *2
Decimal Hexa-
decimal
Reset 0 00 – 3FC
H
000FFFFC
H
Reserved for the system 1 01 – 3F8
H
000FFFF8
H
Reserved for the system 2 02 – 3F4
H
000FFFF4
H
Reserved for the system 3 03 – 3F0
H
000FFFF0
H
Reserved for the system 4 04 – 3EC
H
000FFFEC
H
Reserved for the system 5 05 – 3E8
H
000FFFE8
H
Reserved for the system 6 06 – 3E4
H
000FFFE4
H
Reserved for the system 7 07 – 3E0
H
000FFFE0
H
Reserved for the system 8 08 – 3DC
H
000FFFDC
H
Reserved for the system 9 09 – 3D8
H
000FFFD8
H
Reserved for the system 10 0A – 3D4
H
000FFFD4
H
Reserved for the system 11 0B – 3D0
H
000FFFD0
H
Reserved for the system 12 0C – 3CC
H
000FFFCC
H
Reserved for the system 13 0D – 3C8
H
000FFFC8
H
Undefined instruction exception 14 0E – 3C4
H
000FFFC4
H
NMI request 15 0F F
H
only 3C0
H
000FFFC0
H
External interrupt 0 16 10 ICR00 3BC
H
000FFFBC
H
External interrupt 1 17 11 ICR01 3B8
H
000FFFB8
H
External interrupt 2 18 12 ICR02 3B4
H
000FFFB4
H
External interrupt 3 19 13 ICR03 3B0
H
000FFFB0
H
UART 0 reception completion 20 14 ICR04 3AC
H
000FFFAC
H
UART 1 reception completion 21 15 ICR05 3A8
H
000FFFA8
H