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4.14 DRAM Signal Control Register (DSCR)
[bit 3] C0HE
The C0HE bit controls the CS0H output. When this bit is reset, the output is inhibited.
0: Inhibits output (initial value).
1: Permits output.
[bit 2] C0LE
The C0LE bit controls the CS0L output. When this bit is reset, the output is inhibited.
0: Inhibits output (initial value).
1: Permits output.
[bit 1] RS1E
The RS1E bit controls the RAS1 output. When this bit is reset, the output is inhibited.
In this device type, because the RAS1 pin also serves as the DMAC E0P2 output, it is
controlled together with the EPSE2 and EPDE2 bits of the DMAC control register (DATCR)
as shown below.
[bit 0] RS0E
The RS0E bit controls the RAS0 output. When this bit is reset, the output is inhibited.
0: Inhibits output (initial value).
1: Permits output.
EPSE2 EPDE2 RS1E
0
0
0
1
1
0
0
1
0
1
0
1
X
X
X
Port (initial value)
RAS1 output
E0P2 output
E0P2 output
E0P2 output