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2.8 EIT (Exception, Interrupt, and Trap)
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
Next instruction address --> (SSP)
Interrupt level of accepted request --> ILM
"0" --> S flag
(TBR + vector offset of accepted interrupt request) --> PC
Before executing the first instruction of the handler after the end of an interrupt sequence, the
CPU detects another EIT. If another acceptable EIT is detected, the CPU proceeds to an EIT
processing sequence.
■
Operation for INT Instruction
The operation for the INT #u8 instruction is shown below.
The CPU branches to the interrupt handler of the vector indicated by u8.
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
PC + 2 --> (SSP)
"0" --> I flag
"0" --> S flag
(TBR + 3FC
H
- 4 × u8) --> PC
■
Operation for INTE Instruction
The operation for the INTE instruction is shown below.
The CPU branches to the interrupt handler of the vector with vector number #9.
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
PC + 2 --> (SSP)
"00100" --> ILM
"0" --> S flag
(TBR + 3D8
H
) --> PC
Do not use the INTE instruction in an INTE instruction or step-trace-trap processing routine.
No INTE EIT occurs during step execution.