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CHAPTER 4 BUS INTERFACE
4.17.3 Read Cycles in Each Mode
This section provides read cycle timing charts in each mode.
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Read Cycle Timing Charts
❍
Bus width: 16 bits, access: half-words
Figure 4.17-3 Example 1 of Read Cycle Timing Chart
❍
Bus width: 16 bits, access: bytes
Figure 4.17-4 Example 2 of Read Cycle Timing Chart
❍
Bus width: 8 bits, access: words
Figure 4.17-5 Example 3 of Read Cycle Timing Chart
BA1 BA2 BA1 BA2
CLK
A24-00 #0 #2
D31-24 #0 #2
D23-16 #1 #3
RDX
BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA
CLK
A24-00 #0 #1 #2 #3
D31-24 #0 X #2 X
D23-16 X #1 X #3
RDX
X: Invalid data input
BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2
CLK
A24-00 #0 #1 #2 #3
D31-24 #0 #1 #2 #3
D23-16
RDX