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4.6 Area Mode Register 1 (AMD1)
4.6 Area Mode Register 1 (AMD1)
Area mode register 1 (AMD1) specifies the operation mode of chip select area 1 (area
specified by ASR1 and AMR1).
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Configuration of Area Mode Register 1 (AMD1)
Area mode register 1 (AMD1) is configured as follows:
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Bit Functions of Area Mode Register 1 (AMD1)
[bit 7] MPX (MultiPlex bit)
The MPX bit controls the time sharing I/O interface for address/data input-output.
This device type does not support employing a time sharing I/O bus.
Set this bit to "0".
[bit 4 and 3] BW1 and 0 (Bus Width bit)
BW1 and BW0 specify the bus width of area 1.
[bit 2 to 0] WTC 2 to 0 (Wait Cycle bit)
The WTC bits specify the number of wait cycles to be automatically inserted when the usual
bus interface is operating. Their operation is similar to WTC2 to WTC0 of AMD0; however,
they are reset to "000", and the number of wait cycles to be inserted becomes "0".
76543210
AMD1
0621
H
MPX BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/W
Address: 0000
Initial value
Access
BW1 BW0 Bus width
0
0
1
1
0
1
0
1
8 bits
16 bits
Setting disabled
Reserved