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4.17.17 Hyper DRAM Interface: Read ....................................................................................................... 188
4.17.18 Hyper DRAM Interface: Write ....................................................................................................... 189
4.17.19 Hyper DRAM Interface ................................................................................................................. 190
4.17.20 DRAM Refresh ............................................................................................................................. 191
4.17.21 External Bus Request ................................................................................................................... 193
4.18 Internal Clock Multiplication (Clock Doubler) ..................................................................................... 194
4.19 Program Example for External Bus Operation ................................................................................... 196
CHAPTER 5 I/O PORTS ................................................................................................. 201
5.1 Outline of I/O Ports ............................................................................................................................ 202
5.2 Port Data Register (PDR) .................................................................................................................. 203
5.3 Data Direction Register (DDR) .......................................................................................................... 204
5.4 Using External Pins as I/O Ports ....................................................................................................... 205
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER ........................................ 211
6.1 Overview of External Interrupt/NMI Controller ................................................................................... 212
6.2 Enable Interrupt Request Register (ENIR) ........................................................................................ 213
6.3 External Interrupt Request Register (EIRR) ...................................................................................... 214
6.4 External Level Register (ELVR) ......................................................................................................... 215
6.5 External Interrupt Operation .............................................................................................................. 216
6.6 External Interrupt Request Levels ..................................................................................................... 217
6.7 Nonmaskable Interrupt (NMI) Operation ............................................................................................ 218
CHAPTER 7 DELAYED INTERRUPT MODULE ........................................................... 219
7.1 Overview of Delayed Interrupt Module ............................................................................................. 220
7.2 Delayed Interrupt Control Register (DICR) ........................................................................................ 221
7.3 Operation of Delayed Interrupt Module .............................................................................................. 222
CHAPTER 8 INTERRUPT CONTROLLER .................................................................... 223
8.1 Overview of Interrupt Controller ........................................................................................................ 224
8.2 Interrupt Controller Block Diagram .................................................................................................... 227
8.3 Interrupt Control Register (ICR) ......................................................................................................... 228
8.4 Hold Request Cancel Request Level Setting Register (HRCL) ......................................................... 230
8.5 Priority Check .................................................................................................................................... 231
8.6 Returning from the Standby Mode (Stop/Sleep) ................................................................................ 234
8.7 Hold Request Cancel Request .......................................................................................................... 235
8.8 Example of Using the Hold Request Cancel Request Function (HRCR) ........................................... 236
CHAPTER 9 U-TIMER .................................................................................................... 239
9.1 Overview of U-TIMER ........................................................................................................................ 240
9.2 U-TIMER Registers ............................................................................................................................ 241
9.3 U-TIMER Operation ........................................................................................................................... 243
CHAPTER 10 UART ......................................................................................................... 245
10.1 Overview of UART ............................................................................................................................. 246
10.2 Serial Mode Register (SMR) .............................................................................................................. 248
10.3 Serial Control Register (SCR) ............................................................................................................ 250
10.4 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) .................................... 252