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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
[Example]
Code as follows to use the PLL clock after the clock doubler function is disabled:
[Example]
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Note on Enabling or Disabling the Clock Doubler Function
Enabling or disabling the clock doubler function may cause a dead cycle in the internal clock. A
dead cycle appears as an error if it occurs during time measurement by a timer or UART
transfer.
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Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or
Disabled
Table 3.14.1 lists the operating frequencies of this device that are applicable depending on the
combination of settings in the GCR register and the SLCT1 and SLCT0 bits of the PCTR
DOUBLER-OFF
LDI:20 #GCR,R0
BORL #0001B,@R0 ; Switches to the divide-by-two clock
(CHC = 1)
BANDH #1110B,@R0 ; Disables the clock doubler function
(DBLON = 0)
DOUBLER-OFF
LDI:20 #GCR,R0
BORL #0001B,@R0 ; Switches to the divide-by-two clock
(CHC = 1)
BANDH #1110B,@R0 ; Disables the clock doubler function
(DBLON = 0)
LDI:20 #PCTR,R1
LDI:8 #01000000B,R2
STB R2,@R1 ; PLL=25 MHz
BANDL #1110,@R0 ; Switches to the PLL clock (CHC = 0)