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4.17 Bus Timing
4.17.10 Usual DRAM Read Cycles
This section provides usual DRAM read cycle timing charts.
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Usual DRAM Read Cycle Timing Charts
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Bus width: 16 bits, access: half-words
Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Chart
Q1 Q2 Q3 Q4 Q5
CLK
A24-00 X #0 row.adr. #0 col.adr
D31-24 #0
D23-16 #1
RAS
CAS
WEL
WEH
A24-00 X #0 row.adr. #0 col.adr
D31-24 #0
D23-16 #1
RAS
CASL
CASH
WE
1CAS/2WE
1)
2CAS/1WE
2)