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Figure 7.1-1 Delayed Interrupt Module Register .......................................................................................... 220
Figure 7.1-2 Delayed Interrupt Module Block Diagram ................................................................................ 220
Figure 8.1-1 Interrupt Controller Registers (1/2) .......................................................................................... 225
Figure 8.1-2 Interrupt Controller Registers (2/2) .......................................................................................... 226
Figure 8.2-1 Block Diagram of the Interrupt Controller ................................................................................ 227
Figure 8.8-1 Example of Hardware Configuration for Using the Hold Request Cancel Request Function .. 236
Figure 8.8-2 Example of Timing for Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a) 237
Figure 8.8-3 Example of Timing for Hold Request Cancel Request Sequence
(Interrupt Level: HRCL > a > b) ............................................................................................... 237
Figure 9.1-1 U-TIMER Registers ................................................................................................................. 240
Figure 9.1-2 U-TIMER Block Diagram ......................................................................................................... 240
Figure 9.3-1 Example of Using U-TIMER Channels 0 and 1 in Cascade Mode .......................................... 243
Figure 10.1-1 UART Registers ....................................................................................................................... 246
Figure 10.1-2 UART Block Diagram .............................................................................................................. 247
Figure 10.7-1 Format of Data Transferred in Asynchronous (Start-Stop) Mode (Mode 0 or 1) ..................... 257
Figure 10.8-1 Format of Data Transferred in CLK Synchronous Mode (Mode 2) .......................................... 258
Figure 10.9-1 ORE, FRE, and RDRF Set Timing (Mode 0) ........................................................................... 260
Figure 10.9-2 ORE, FRE, and RDRF Set Timing (Mode 1) ........................................................................... 261
Figure 10.9-3 ORE and RDRF Set Timing (Mode 2) ..................................................................................... 261
Figure 10.9-4 TDRE Set Timing (Mode 0 or 1) .............................................................................................. 262
Figure 10.9-5 TDRE Set Timing (Mode 2) ..................................................................................................... 262
Figure 10.10-1 Sample System Structure for Mode 1 ...................................................................................... 263
Figure 10.10-2 Communication Flowchart for Mode 1 ..................................................................................... 264
Figure 11.1-1 A/D Converter Registers ......................................................................................................... 268
Figure 11.1-2 Block Diagram of the A/D Converter. ...................................................................................... 269
Figure 11.5-1 Workflow of the Data Protection Function when DMA Transfer is Used ................................. 279
Figure 12.1-1 16-Bit Reload Timer Registers ................................................................................................ 282
Figure 12.1-2 16-Bit Reload Timer Block Diagram ........................................................................................ 283
Figure 12.4-1 Counter Start and Operation Timing ........................................................................................ 287
Figure 12.4-2 Underflow Operation Timing .................................................................................................... 288
Figure 12.5-1 Counter States Transition ........................................................................................................ 289
Figure 13.1-1 Bit Search Module Registers ................................................................................................... 292
Figure 13.1-2 Block Diagram of the Bit Search Module ................................................................................. 292
Figure 14.1-1 PWM Timer Registers ............................................................................................................. 301
Figure 14.2-1 General Block Diagram of PWM Timer ................................................................................... 302
Figure 14.2-2 Block Diagram of Single PWM Timer Channel ........................................................................ 303
Figure 14.9-1 PWM Operation Timing Chart (Trigger Restart Disabled) ....................................................... 316
Figure 14.9-2 PWM Operation Timing Chart (Trigger Restart Enabled) ........................................................ 316