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148
CHAPTER 4 BUS INTERFACE
❍
Half-word access (during execution of LDUH and STH instructions)
Figure 4.16-12 Relationship between Internal Register and External Data Bus for Half-word Access
❍
Byte access (during execution of LDUB and STB instructions)
Figure 4.16-13 Relationship between Internal Register and External Data Bus for Byte Access
BB
AA
AA
BB
D31
D07
D15
D23
D31
D23
Internal register External bus
AA
AA
D31
D23
D15
D07
D31
D23
AA
AA
D31
D31
D23
D15
D07
D23
(a) Lower bits of output address "0" (b) Lower bits of output address "1"
Internal register External bus Internal register External bus