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INDEX
W
wait cycle ............................................................. 159
watchdog controller block diagram ........................ 99
watchdog timer reset delay register (WPR), bit
function of .................................................... 85
watchdog timer reset delay register (WPR),
configuration of ............................................ 85
watchdog timer, starting .........................................99
word access..........................................141, 147, 151
write cycle timing chart .........................................168
write timing chart, hyper DRAM interface .............189
write timing chart. single DRAM interface.............186
writing by ROM writer ...........................................353