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CHAPTER 4 BUS INTERFACE
4.17.4 Write Cycles in Each Mode
This section provides write cycle timing charts in each mode.
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Write Cycle Timing Chart
❍
Bus width: 16 bits, access: words
Figure 4.17-8 Example 1 of Write Cycle Timing Chart
❍
Bus width: 16 bits, access: half-words
Figure 4.17-9 Example 2 of Write Cycle Timing Chart
❍
Bus width: 16 bits, access: bytes
Figure 4.17-10 Example 3 of Write Cycle Timing Chart
BA1 BA2 BA1 BA2
CLK
A24-00 #0 #2
D31-24 #0 #2
D23-16 #1 #3
WR0X
WR1X
BA1 BA2 BA1 BA2
CLK
A24-00 #0 #2
D31-24 #0 #2
D23-16 #1 #3
WR0X
WR1X
BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA
CLK
A24-00 #0 #1 #2 #3
D31-24 #0 X #2 X
D23-16 X #1 X #3
WR0X
WR1X
X: Invalid data input