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15.8 Notes on DMAC
15.8 Notes on DMAC
This section provides notes on using the DMAC.
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Interchannel Priority Order
Once the DMAC starts with a DMA transfer request from one channel, DMA transfer requests
from another channel are suspended until the current transfer ends.
When the DMAC detects DMA transfer requests from multiple channels which are active
simultaneously, these requests are accepted in the following priority order:
(High) ch 0> ch 1 > ch 2 > ch 3 > ch 4> ch 5> ch 6 > ch 7 (low)
Even when two or more channels issue DMA transfer requests simultaneously, DMA transfer is
performed for only one channel. After that, bus control returns to the CPU before performing
the DMA transfer for the next channel.
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When Using a Resource Interrupt Request as a DMA Transfer Request
For performing a transfer by the DMAC, the interrupt level in the interrupt controller must be set
to the interrupt inhibition level.
When an interrupt is to be generated, the DMAC operation enable bit in the DMAC must be set
to disabled and the interrupt level must be set to an appropriate value.
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Suppression of DMA Transfer for an Interrupt with a Higher Priority
If during DMA transfer in response to a DMA transfer request an interrupt request with a higher
priority arrives, the MB91F109 can stop the DMA transfer.
❍
HRCL register
For stopping a DMA transfer operation in response to an interrupt request, use the hold request
cancel level register (HRCL).
If the interrupt level for an interrupt request issued from a peripheral circuit is higher than that
set in the HRCL, the DMA transfer operation by the DMAC is suppressed. If the DMA transfer
operation is already in progress, it stops at this point in time and releases bus control to the
CPU. All DMA transfer requests generated in DMA transfer request wait state are suspended.
When the HRCL is reset to the lowest level (31), the DMA transfer operation is suppressed for
every interrupt request. For continuing DMA transfer even if an interrupt request is issued, the
HRCL register must be set to the appropriate value.