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CHAPTER 4 BUS INTERFACE
edge of CASL or CASH for the 2CAS/1WE.
For the 1CAS/2WE, CAS corresponds to D31 to D16. For the 2CAS/1WE, CASL
corresponds to D31 to D24, and CASH corresponds to D23 to D16.
In read cycles, all of D31 to D16 are fetched, irrespective of the bus width and word, half-
word, and byte access. Whether the read data is valid is determined inside the chip.
• RAS is a row address strobe signal, which becomes "H" at the falling edge of Q1 and "L" at
the rising edge of Q3. When the PAGE bit is "0" (non-high-speed page mode), RAS
becomes Normally H.
• CAS is a column address strobe signal. CASL of the 2CAS/1WE represents CAS of the
upper address side ("0" of the lower 1 bit), and CASH represents that of the lower address
side ("1" of the lower 1 bit).
This signal is asserted at the falling edge of Q4 and negated at the falling edge of Q5.
• In read cycles, WE
(including WEL and WEH) is negated.
• In read cycles, RDX stays at "L" from the Q1 cycle.
• CS4X and CS5X are output from the rising edge of the Q1 cycle.
• DACK0 to DACK2 and E0P0 to E0P2 are output in external bus cycles. Whether to output
these signals is determined by DMAC register settings. The output time is the same as for
CAS.