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CHAPTER 15 DMAC
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Continuous Transfer Mode
1. The initialization routine sets the descriptor.
2. The program initializes the DMA transfer request source. Set the external transfer request
input pin to the H-level or L-level detection mode.
3. The program sets the target DOEn bit of the DACSR to 1.
--- This completes the setting for DMA. ---
4. Upon detection of a DMA transfer request input, the DMAC requests bus control right from
the CPU.
5. When the bus control right is transferred from the CPU, the DMAC accesses three words of
information of the descriptor through the bus.
6. While decrementing DMACT, the DMAC performs a transfer only once based on the
information stored in the descriptor. The DMAC outputs a transfer request acknowledgment
signal during data transfer. When decremented DMACT reaches 0, the DMAC outputs a
transfer end signal during data transfer.
7. If the DMACT value is not 0 and a DMA request from a peripheral device remains, the
DMAC repeats step 6) (via step 8) depending on the bus status).
8. When the DMACT value is 0 or the DMA requests from peripheral devices are canceled, the
DMAC increments or decrements SADR or DADR and writes the result together with the
DMACT value back to the descriptor.
9. The DMAC returns the bus control right to the CPU.
10.If the DMACT value is 0, the DMAC sets DACSR DEDn to 1 and causes an interrupt to the
CPU if interrupts have been enabled.
The number of minimum required cycles per transfer is shown below (on the assumption that
the descriptor is stored in built-in RAM, data is transferred between external busses and the
data length is counted in bytes):
• When both transfer source and destination addresses are fixed: (6 + 5 × n) cycles
• When either the transfer source or destination are fixed: (7 + 5 × n) cycles
• When both transfer source and destination addresses are incremented or decremented: (8+
5 × n) cycles