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APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-125
A-1
A-ap
A.5 SRAM (70ns)
SRAM interface setup examples – 70ns
Operating Read cycle Output disable
frequency Wait cycle Read cycle
Write cycle
delay cycle
20MHz 2 3 3 1.5
25MHz 2 3 3 1.5
33MHz 3 4 4 1.5
SRAM interface timing – 70ns
SRAM interface 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 70 – 4 120 3 1203150
Address access time tACC –70412031203150
#CE access time tACS –70412031203150
#OE access time tOE –403.51052.51002.5125
Output disable delay time tOHZ 0301.545 1.5 60 1.5 75
<Write cycle>
Write cycle time tWC 70 – 4 120 3 1203150
Address enable time tAW 60 – 3.5 105 2.5 100 2.5 125
Write pulse width tWP 55 – 3 90 2 80 2 100
Input data setup time tDW 30 – 3 90 2 80 2 100
Input data hold time tDH 0–0.5150.520 0.5 25
SRAM: 70ns, CPU: 33MHz, read cycle
t
RC
t
ACC
t
ACS
t
OE
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
t
OHZ
SRAM: 70ns, CPU: 33MHz, write cycle
tWC
tAW
tWP
tDW
BCLK
A[23:0]
#CEx
#WR
D[15:0]
WR data
tDH