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V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-21
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D0MOD1
D0MOD0
D0IN1
D0IN0
D0ADRH11
D0ADRH10
D0ADRH9
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer mode
D) Ch.0 destination address
control
S) Invalid
D) Ch.0 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004822A
(HW)
High-speed
DMA Ch.0
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D0MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS0_EN
DF–1
D0
reserved
Ch.0 enable
1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004822C
(HW)
High-speed
DMA Ch.0
enable register
––
HS0_TF
DF–1
D0
reserved
Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading)
1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004822E
(HW)
High-speed
DMA Ch.0
trigger flag
register
TC1_L7
TC1_L6
TC1_L5
TC1_L4
TC1_L3
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
BLKLEN16
BLKLEN15
BLKLEN14
BLKLEN13
BLKLEN12
BLKLEN11
BLKLEN10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer c
ounter[7:0]
(block transfer mode)
Ch.1 transfer counter[15:8]
(single/successive transfer mode)
Ch.1 block length
(block transfer mode)
Ch.1 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048230
(HW)
High-speed
DMA Ch.1
transfer
counter
register
–
–
DUALM1
D1DIR
–
TC1_H7
TC1_H6
TC1_H5
TC1_H4
TC1_H3
TC1_H2
TC1_H1
TC1_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 address mode selection
D) Invalid
S) Ch.1 transfer direction control
reserved
Ch.1 transfer counter[15:8]
(block transfer mode)
Ch.1 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048232
(HW)
High-speed
DMA Ch.1
control register
Note:
D) Dual address
mode
S) Single
address
mode