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II CORE BLOCK: ITC (Interrupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-3
A-1
B-II
ITC
Interrupt Factors and Intelligent DMA
Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors
occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated
after IDMA is completed. (The interrupt request can be disabled by a program.)
IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation".
Nonmaskable Interrupt (NMI)
The nonmaskable interrupt (NMI) can be generated by pulling the #NMI pin low or using the internal watchdog
timer. The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes.
This interrupt is prioritized over other interrupts and is unconditionally accepted by the CPU.
However, since this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked
in hardware until a write to the SP is completed after an initial reset.
Interrupt Processing by the CPU
The CPU keeps sampling interrupt requests every cycle. When the CPU accepts an interrupt request, it enters trap
processing after completing execution of the instruction that was being executed.
The following lists the contents executed in trap processing.
(1) The PSR and the current program counter (PC) value are saved to the stack.
(2) The IE bit of the PSR is reset to "0" (following maskable interrupts are disabled).
(3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level
changed).
(4) The vector of the generated interrupt factor is loaded into the PC, thus executing the interrupt processing
routine.
Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts
can also be handled by setting the IE bit to "1" in the interrupt processing routine. In this case, since the IL has
been changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is
accepted.
When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status
before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one
that was being executed when the interrupt occurred.
Clearing Standby Mode by Interrupts
The standby modes (HALT and SLEEP) are cleared by an NMI or a maskable interrupt.
All maskable interrupts can be used to clear HALT mode. However, if the bus clock has stopped in HALT2 mode,
a DMA interrupt cannot be used.
In SLEEP mode, since the high-speed (OSC3) oscillation circuit is deactivated, interrupts from the peripheral
circuits that operate with the OSC3 clock cannot be used.
Interrupts that can be used to clear basic HALT mode: NMI and all maskable interrupts
Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts)
Interrupts that can be used to clear SLEEP mode: NMI, input port interrupts, and clock timer interrupts
Clearing of the standby modes is accomplished by an interrupt request to the CPU. Therefore, this requires that the
PSR be set in such a way that the requested interrupt will be accepted, and that the interrupt enable register for the
interrupt factor be set to accept the interrupt.
When standby mode is cleared and the CPU has accepted the interrupt, it returns to the instruction next to the halt
or slp instruction after executing the interrupt processing routine.
Note: If the interrupt factor used to restart from the standby mode has been set to invoke the IDMA, the
IDMA is started up by that interrupt.
In the case of SLEEP mode, the high-speed (OSC3) oscillation circuit also starts operating.
If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side,
no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next
interrupt request is generated.