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II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-5
A-1
B-II
CLG
Power-Control Register Protection Flag
The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU
operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary
writing.
To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control
protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control
register (0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is
written to. Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is
written to.
The flag CLGP[7:0] does not affect the readout from the power-control register (0x40180).
Operation in Standby Mode
In HALT mode, which is entered by executing the halt instruction, the high-speed (OSC3) and low-speed (OSC1)
oscillation circuits both retain their status before HALT mode is entered. Under normal conditions, therefore, there
is no need to control the oscillation circuits before entering or after exiting HALT mode.
The high-speed (OSC3) oscillation circuit stops operating after SLEEP mode is entered, which is done by
executing the slp (sleep) instruction. If the high-speed (OSC3) oscillation circuit was operating before SLEEP
mode was entered, it automatically starts oscillating again after SLEEP mode is exited.
In addition, if the CPU was operating using the OSC3 clock before SLEEP mode was entered, the CPU starts
operating using the OSC3 clock again even after SLEEP mode is exited. The high-speed (OSC3) oscillation circuit
requires 10 ms max. (when using a 3.3-V crystal resonator) for its oscillation to stabilize after oscillation starts. To
prevent the CPU from operating erratically upon restart during this period, the C33 Core Block is designed to allow
the OSC3 clock supply to the CPU to be disabled in the hardware after SLEEP mode is exited. Use 8T1ON (D2) /
Clock option register (0x40190) to select this function. Use 8-bit programmable timer 1 to set the waitting time
before clock supply is started.
The processing procedure and the operations to be performed when this function is used are as follows:
1. Disable the 8-bit programmable timer 1 interrupt.
2. Preset the initial count to 8-bit programmable timer 1.
Set a value that will provide an ample stabilization waiting time. It is also necessary to set the input clock for 8-
bit programmable timer 1 using the prescaler.
3. Enable the interrupt used to exit SLEEP mode.
Before enabling the interrupt, be sure to reset the interrupt factor flag.
4. Write "0" to 8T1ON (turn on the function for waiting until the oscillation stabilizes after exiting SLEEP mode).
5. Activate 8-bit programmable timer 1 to start counting.
6. Enter SLEEP mode using the slp instruction.
:
SLEEP mode
:
7. Exit SLEEP mode using an NMI, input port, or timer interrupt.
8. The high-speed (OSC3) oscillation circuit starts oscillating when SLEEP mode is exited. 8-bit programmable
timer 1 also is made to start counting using the OSC3 clock.
9. 8-bit programmable timer 1 underflows.
The operating clock supply to the CPU is begun by the underflow signal, so that the CPU restarts.
For details on how to control the 8-bit programmable timer, prescaler, and interrupts, refer to the description of
each item in this manual.
Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective
only when SLEEP mode is exited.
Writing to 8T1ON is effective only when the power-control register protection flag is set to
"0b10010110".