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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-15
A-1
B-VI
SDRAM
Burst Read Cycle
Except when the burst length is set to 1 (SDRBL[1:0] ≠ "00"), the SDRAM controller always reads data from the
SDRAM in bursts.
Figure 2.11 shows several examples of timing charts when reading out 4-word data from the same row address in
varying burst lengths.
Example of parameter settings: CAS latency = 2, t
RCD = 2 cycles, tRP = 2 cycles
(1) Burst length = 8
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ
BA BA
ROW
D(1) D(2) D(3) D(4) D(5) D(6)
tRCDtRP CAS latency
= 2
ROW COL
BA
(2) Burst length = 4
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ
BA BA
ROW
D(1) D(2) D(3) D(4)
tRCDtRP CAS latency
= 2
ROW COL
BA
(3) Burst length = 2
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ NOP READ
BA BA
ROW
D(1-1) D(1-2) D(2-1) D(2-2)
tRCDtRP CAS latency
= 2
CAS latency
= 2
ROW COL1
BA
COL2
BA
Figure 2.11 Burst Read in the Same Page