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II CORE BLOCK: ITC (Interrupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-19
A-1
B-II
ITC
Fxxx: Interrupt factor flag
Indicate the status of interrupt factors generated.
When read
Read "1": Interrupt factor generated
Read "0": No interrupt factor generated
When written using the reset-only method (default)
Write "1": Factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Factor flag is set
Write "0": Factor flag is reset
The interrupt factor flag is set to "1" when an interrupt factor occurs in each peripheral circuit.
If the following conditions are met at this time, an interrupt is generated to the CPU:
1. The corresponding bit of the interrupt enable register is set to "1".
2. No other interrupt request of higher priority has occurred.
3. The IE bit of the PSR is set to "1" (interrupt enabled).
4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).
When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt
request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of
IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.
The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and
interrupt priority registers are set.
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and
the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and
setting the IE bit to "1" or executing the reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set
up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to
confuse these two conditions.
The interrupt factor flag becomes indeterminate when initially reset, so be sure to reset the flag in the software
application.
Rxxx: IDMA request register
Specify whether or not to invoke IDMA when an interrupt factor occurs.
When using the set-only method (default)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA request
Write "0": Interrupt request
Read: Valid
If a bit of this register is set to "1", IDMA is invoked when the corresponding interrupt factor occurs and the
programmed data transfer is performed. If the register bit is set to "0", regular interrupt processing is performed,
without ever invoking IDMA.
For details about IDMA, refer to "IDMA (Intelligent DMA)".
If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion
of DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that
enabled IDMA invoking is generated.
After an initial reset, this register is set to "0" (Interrupt is requested).