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V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-36 EPSON S1C33L03 FUNCTION PART
Programming Notes
(1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0").
(2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the
flag to prevent interrupts or IDMA requests from being generated inadvertently.
(3) To prevent an interrupt from being generated repeatedly for the same factor, be sure to reset the interrupt
factor flag before setting up the PSR again or executing the reti instruction.
(4) HSDMA is given higher priority over IDMA (intelligent DMA) and the CPU. However, since HSDMA and
IDMA share the same circuit, HSDMA cannot gain the bus ownership while an IDMA transfer is under way.
Requests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the
IDMA transfer is completed.
A request for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are
accepted after completion of the HSDMA transfer.
(5) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a setting of 0 in clock option register HLT2OP (D3/0x40190), that operation will be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.