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V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-34 EPSON S1C33L03 FUNCTION PART
EHDM0: Ch. 0 interrupt enable (D0) / DMA interrupt enable register (0x40271)
EHDM1: Ch. 1 interrupt enable (D1) / DMA interrupt enable register (0x40271)
EHDM2: Ch. 2 interrupt enable (D2) / DMA interrupt enable register (0x40271)
EHDM3: Ch. 3 interrupt enable (D3) / DMA interrupt enable register (0x40271)
Enable or disable interrupt generation to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
EHDMx is the interrupt enable bit for HSDMA channel x. The interrupt is enabled when EHDMx is set to "1" and
disabled when EHDMx is set to "0".
At initial reset, EHDMx is set to "0" (interrupt disabled).
FHDM0: Ch. 0 interrupt factor flag (D0) / DMA interrupt factor flag register (0x40281)
FHDM1: Ch. 1 interrupt factor flag (D1) / DMA interrupt factor flag register (0x40281)
FHDM2: Ch. 2 interrupt factor flag (D2) / DMA interrupt factor flag register (0x40281)
FHDM3: Ch. 3 interrupt factor flag (D3) / DMA interrupt factor flag register (0x40281)
Indicate the occurrence status of HSDMA interrupt factor.
When read
Read "1": Interrupt factor generated
Read "0": No interrupt factor generated
When written using the reset-only method (default)
Write "1": Factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Factor flag is set
Write "0": Factor flag is reset
FHDMx is the interrupt factor flag for HSDMA channel x. These flags are set to "1" when the transfer counter
reaches 0. An interrupt to the CPU is generated if the following conditions are met at this time:
1. The corresponding interrupt enable register is set to "1".
2. No other interrupt request of higher priority is generated.
3. The IE bit of the PSR is set to "1" (interrupt enable).
4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).
When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt
request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of
the IDMA side, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.
The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and
interrupt priority registers are set.
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and
the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and
setting the IE bit to "1" or executing the reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set
up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to
confuse these two cases.
The FHDMx flag becomes indeterminate when initially reset, so be sure to reset the flag in the software
application.