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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-27
A-1
B-VI
SDRAM
SDRPC1:#CE8/14 pin configuration (D2) / SDRAM area configuration register (0x39FFC0)
SDRPC0:#CE7/13 pin configuration (D3) / SDRAM area configuration register (0x39FFC0)
Set the chip-enable pin for an SDRAM.
Write "1": #SDCEx (for SDRAM)
Write "0": #CExx (for other devices)
Read: Valid
Select the pin to be used as a chip enable for the SDRAM connected to the S1C33. Write "1" to SDRPC0 to set the
#CE7/13 pin for SDRAM use (#SDCE0). Similarly, write "1" to SDRPC1 to set the #CE8/14 pin for SDRAM use
(#SDCE1). Writing "0" to either bit sets the corresponding pin to be used as chip-enable output for other devices.
SDRAMs and the BCU are used differently—with SDRAMS, the areas and the pins used are not associated with
each other. Consequently, when using area 7 for an SDRAM, for example, it is possible to use #CE8/14 as the
chip-enable pin for the SDRAM. Or while using both areas 7 and 8, it is possible to use only #CE7/13 as the chip-
enable pin. See Table 2.5 for the combinations of areas and pins used.
At cold start, these bits are set to "0" (#CExx). At hot start, these bits retain their status before being initialized.
SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1)
Enable the pins used for the SDRAM.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM
clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions.
The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
At cold start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized.
SDRINI: Initialize SDRAM (D6) / SDRAM control register (0x39FFC1)
Initiate the SDRAM initialization sequence.
Write "1": Start
Write "0": No operation
Read: Valid
Writing "1" to SDRINI initiates the SDRAM initialization sequence at SDRAM power-up, as specified by SDRIS
(D4/0x39FFC1). This operation must be performed after holding the SDRAM in an NOP state for at least 100 µs
(this varies with each SDRAM) after powering up the SDRAM.
At cold or hot start, SDRINI is set to "0".
SDRSRF: Enable SDRAM self-refresh (D5) / SDRAM control register (0x39FFC1)
Enable the SDRAM's self-refresh control function.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Writing "1" to SDRSRF enables the SDRAM controller to start self-refreshing the SDRAM (by setting SDCKE
output low). Note that self-refreshing of the SDRAM actually begins a certain time after accessing or auto-
refreshing the SDRAM. The duration of this elapsed time is defined by the number of clock cycles in
SDRSRFC[3:0] (D[3:0]/0x39FFC8).
SDRSRF = "0" disables the self-refresh function.
At cold start, SDRSRF is set to "0" (disabled). At hot start, SDRSRF retains its status before being initialized.