Filter
Top Products
II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-6 EPSON S1C33L03 FUNCTION PART
The IL is rewritten for only maskable interrupts and not for any other traps (except a reset).
The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset.
Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15.
However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in
each interrupt system can only be set for up to 8.
Interrupt Factor Flag and Interrupt Enable Register
An interrupt factor flag and an interrupt enable register are provided for each maskable interrupt factor.
Interrupt factor flag
The interrupt factor flag is set to "1" when the corresponding interrupt factor occurs. Reading the flag enables
you to determine what caused an interrupt, making it unnecessary to resort to the CPU's trap processing. The
interrupt factor flag is reset by writing data in software or by IDMA operation. Note that the method by which
this flag is reset can be selected from the software application using either of the two methods described
below. This selection is accomplished using RSTONLY (D0) / Flag set/reset method select register
(0x4029F).
• Reset-only method (default)
This method is selected (RSTONLY = "1") when initially reset.
With this method, the interrupt factor flag is reset by writing "1". Although multiple interrupt factor flags are
located at the same address of the interrupt control register, the interrupt factor flags for which "0" has been
written can be neither set nor reset. Therefore, this method ensures that only a specific factor flag is reset.
However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an interrupt factor
flag that has been set to "1" is reset by writing.
In this method, no interrupt factor flag can be set in the software application.
• Read/write method
This method is selected by writing "0" to RSTONLY.
When this method is used, interrupt factor flags can be read and written as for other registers. Therefore, the
flag is reset by writing "0" and set by writing "1". In this case, all factor flags for which "0" has been written
are reset. Even in a read-modify-write operation, an interrupt factor can occur between the read and the write,
so be careful when using this method.
Since interrupt factor flags are not initialized by an initial reset, be sure to reset them before enabling
interrupts.
Note: Even when a maskable interrupt request is accepted by the CPU and control branches off to the
interrupt processing routine, the interrupt factor flag is not reset. Consequently, if control is
returned from the interrupt processing routine by the reti instruction without resetting the interrupt
factor flag in a program, the same interrupt factor occurs again.
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in
this manual.