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III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-19
A-1
B-III
SIF
Note:The receive operation is terminated when the first stop bit is sampled even if the stop bit is
configured with two bits.
•Successive receive operations
When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1"
(buffer full), indicating that the received data can be read out. Thereafter, data can be received successively
because the receive data register can be read out while the next data is received. The procedure for receiving
is described above.
When RDBFx is set to "1", a receive-data full interrupt factor occurs. Since an interrupt can be generated as
set by the interrupt controller, the received data can be read using an interrupt processing routine. In addition,
since this interrupt factor can be used to invoke IDMA, the received data can be received successively in
locations prepared in memory through DMA transfers.
For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA".
(3) Receive errors
Three types of receive errors can be detected when receiving data in the asynchronous mode.
Since an interrupt can be generated by setting the interrupt controller, the error can be processed using an
interrupt processing routine. For details on receive error interrupts, refer to "Serial Interface Interrupts and
DMA".
•Parity error
If EPRx is set to "1" (parity added), the parity is checked when data is received.
This parity check is performed when the data received in the shift register is transferred to the receive data
register in order to check conformity with PMDx settings (odd or even parity). If any nonconformity is found
in this check, a parity error is assumed and the parity error flag is set to "1".
Ch.0 parity error flag: PER0 (D3) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 parity error flag: PER1 (D3) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 parity error flag: PER2 (D3) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 parity error flag: PER3 (D3) / Serial I/F Ch.3 status register (0x401F7)
Even when this error occurs, the received data in error is transferred to the receive data register and the
receive operation is continued. However, the content of the received data for which a parity error is flagged
cannot be guaranteed.
The PERx flag is reset to "0" by writing "0".
•Framing error
If data with a stop bit = "0" is received, the serial interface assumes that the data is out of synchronization and
generates a framing error.
If two stop bits are used, only the first stop bit is checked.
When this error occurs, the framing-error flag is set to "1".
Ch.0 framing-error flag: FER0 (D4) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 framing-error flag: FER1 (D4) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 framing-error flag: FER2 (D4) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 framing-error flag: FER3 (D4) / Serial I/F Ch.3 status register (0x401F7)
Even when this error occurs, the received data in error is transferred to the receive data register and the
receive operation is continued. However, the content of the received data for which a framing error is flagged
cannot be guaranteed, even if no framing error is found in the following data received.
The FERx flag is reset to "0" by writing "0".