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III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-11
A-1
B-III
CTM
ECTM: Clock timer interrupt enable (D1) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277)
Enables or disables generation of an interrupt to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
This bit controls the clock timer interrupt. The interrupt is enabled by setting ECTM to "1" and is disabled by
setting it to "0".
At initial reset, ECTM is set to "0" (interrupt disabled).
FCTM:
Clock timer interrupt factor flag (D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Indicates whether the clock timer interrupt factor has occurred.
When read
Read "1": Interrupt factor has occurred
Read "0": No interrupt factor has occurred
When written using the reset-only method (default)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
FCTM is set to "1" when the selected interrupt factor or alarm factor occurs.
At this time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher interrupt priority is generated.
3. The IE bit of the PSR is set to "1" (interrupt enabled).
4. The corresponding interrupt priority register is set to a value higher than the CPU interrupt level (IL).
The interrupt factor flag is always set to "1" when an interrupt factor occurs, no matter how the interrupt enable and
interrupt priority registers are set.
For the next interrupt to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
generated interrupts (or if the reti instruction is executed) without the interrupt factor flag being reset, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used.
The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software.