Filter
Top Products
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
B-VI-2-32 EPSON S1C33L03 FUNCTION PART
Programming Notes
(1) Make sure that two wait cycles are inserted when accessing area 6, where the SDRAM controller is allocated.
With any other number of specified wait cycles, data may not be written normally to the SDRAM control
registers.
(2) Set the area used for an SDRAM for internal access (A8IO (DA/0x48132) = "1" or A14IO (DD/0x48132) =
"1").
(3) Before entering HALT2 or SLEEP mode, be sure to place the SDRAM in self-refresh mode, because the
SDRAM cannot be auto-refreshed while in those modes. In that case, confirm that SDRSRM
(D6/0x39FFCA) = "0" (i.e., that the SDRAM is in self-refresh mode) before executing the HALT or SLP
instruction.
If an access to the SDRAM occurs while being self-refreshed, the SDRAM is taken out of self-refresh mode;
thus always make sure the SDRAM check and the HALT/SLP instruction execution are performed from
devices other than the SDRAM.
(4) Do not access addresses 0x039FFCB to 0x039FFCD, as the user program will not be able to control the CPU.
(5) If the program accesses an area out of the address range set using the address setting register (0x39FFC2), an
unintended area is accessed and the stored data may be overwritten. Therefore, do not access an area out of
the set range.