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V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-15
A-1
B-V
IDMA
DBASEL[15:0]: IDMA base address [15:0] (D[F:0]) / IDMA base address low-order register (0x48200)
DBASEH[11:0]: IDMA base address [27:16] (D[B:0]) / IDMA base address high-order register (0x48202)
Specify the starting address of the control information to be placed in RAM.
Use DBASEL to set the 16 low-order bits of the address and DBASEH to set the 12 high-order bits.
The address to be set in these registers must always be a word (32-bit) boundary address.
These registers cannot be read or written in bytes. The registers must be accessed in words for read/write
operations to address 0x48200, and in half-words for read/write operations to addresses 0x48200 and 0x48202.
Write operations in half-words must be performed in order of 0x48200 and 0x48202. Read operations in half-
words may be performed in any order.
Write operations to the IDMA base address registers during a DMA transfer are ignored. When the register is read
during a DMA transfer, the read data is indeterminate.
At initial reset, the base address is set to 0xC003A0.
IDMAEN: DMA enable (D0) / DMA enable register (0x48205)
Enable a IDMA transfer.
Write "1": Enabled
Write "0": Disabled
Read: Valid
A data transfer operation by intelligent DMA is enabled by writing "1" to IDMAEN.
IDMA transfer is disabled by writing "0" to IDMAEN.
At initial reset, IDMAEN is set to "0" (disabled).
DCHN[6:0]: IDMA channel number (D[6:0]) / IDMA start register (0x48204)
Set the channel numbers (0 to 127) to be invoked by a trigger in the software application.
At initial reset, DCHN is set to "0".
DSTART: IDMA start (D7) / IDMA start register (0x48204)
Use this register for a trigger in the software application and for monitoring the operation of IDMA.
When written
Write "1": IDMA started
Write "0": Invalid
When read
Read "1": IDMA operating (only when invoked by software trigger)
Read "0": IDMA inactive
When DSTART is set to "1", it functions as a trigger in the software application, invoking the IDMA channel that
is set in the DCHN register.
At initial reset, DSTART is set to "0".
PDM2–PDM0: IDMA interrupt level (D[2:0]) / IDMA interrupt priority register (0x40265)
Set the priority level of the interrupt upon completion of IDMA transfer in the range of 0 to 7.
At initial reset, the contents of this register are indeterminate.
EIDMA: IDMA interrupt enable (D4) / DMA interrupt enable register (0x40271)
Enable or disable occurrence of an interrupt to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
This bit controls the interrupt generated upon completion of IDMA transfer. The interrupt is enabled by setting this
bit to "1" and disabled by setting this bit to "0".
At initial reset, EIDMA is set to "0" (interrupt disable).