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V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-3
A-1
B-V
IDMA
BLKLEN[7:0]: Block size/transfer counter (D[7:0]/1st Word)
In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In
single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here.
Note: The transfer count and block size thus set are decremented according to the transfers performed.
If the transfer count or block size is set to 0, it is decremented to all Fs by the first transfer
performed. This means that you have set the maximum value that is determined by the number of
bits available.
DINTEN: End-of-transfer interrupt enable (D31/2nd Word)
If this bit is left set (= "1"), when the transfer counter reaches 0, an interrupt request to the CPU is generated
based on the interrupt factor flag by which IDMA has been invoked.
If this bit is "0", no interrupt request to the CPU is generated even when the transfer counter has reached 0.
DATSIZ: Data size control (D30/2nd Word)
Set the unit size of data to be transferred.
A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0".
SRINC[1:0]: Source address control (D[29:28]/2nd Word)
Set the source address updating format.
If the format is set for "address fixed" (00), the source address is not changed by a data transfer performed.
Even when transferring multiple data, the transfer data is always read from the same address.
If the format is set for "address increment" (11 or 10) in single and successive transfer modes, the source
address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is
completed. If the format is set for "address decrement" (01), the source address is decremented in the same
way.
In block transfer mode too, the source address is incremented or decremented when one data unit is
transferred. However, if the set format is "10", the source address that has been incremented during a block
transfer recycles back to the initial value when the block transfer is completed.
SRADR[27:0]: Source address (D[27:0]/2nd Word)
Use these bits to set the starting address at the source of transfer. The content set here is updated according to
the setting of SRINC.
DMOD[1:0]: Transfer mode (D[31:30]/3rd Word)
Use these bits to set the desired transfer mode.
The transfer modes are outlined below (to be detailed later):
• Single transfer mode (00)
In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of
the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
• Successive transfer mode (01)
In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer
counter. The transfer counter is decremented to 0 each time data is transferred.
• Block transfer mode (10)
In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data
of the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the
transfer counter, an equal number of triggers are required.