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III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-9
A-1
B-III
SIF
3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the
LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted.
4. The #SRDYx signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin.
The master device must take in each bit synchronously with the rising edges of the synchronizing clock.
•Successive transmit operations
When the data in the transmit data register is transferred to the shift register, TDBEx is reset to "1" (buffer
empty). Once this occurs, the next transmit data can be written to the transmit data register, even during data
transmission.
This allows data to be transmitted successively. The transmit procedure is described above.
When TDBEx is set to "1", a transmit-data empty interrupt factor occurs. Since an interrupt can be generated
as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing
routine. In addition, since this interrupt factor can be used to invoke DMA, the data prepared in memory can
be transmitted successively to the transmit-data register through DMA transfers.
For details on how to control interrupts and DMA requests, refer to "Serial Interface Interrupts and DMA".
(3) Terminating transmit operation
Upon completion of data transmission, write "0" to the transmit-enable bit TXENx to disable transmit
operation.
Receive control
(1) Enabling receive operation
Use the receive-enable bit RXENx for receive control.
Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.3 control register (0x401F8)
When receive operations are enabled by writing "1" to this bit, clock input to the shift register is enabled
(ready for input), thereby starting a data-receive operation. The synchronizing clock input/output on the
#SCLKx pin also is enabled (ready for input/output). Receive operations are disabled by writing "0" to
RXENx.
After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK
pins are changed at follows:
#SRDY: When slave mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
#SCLK: When master mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so
the communication mode is half-duplex. Therefore, RXENx and transmit-enable bit TXENx cannot
be enabled simultaneously. When receiving data, fix TXENx at "0" and do not change it during a
receive operation. In addition, make sure RXENx is not set to "0" during a receive operation.
(2) Receive procedure
This serial interface has a receive shift register and a receive data register (receive data buffer) that are
provided independently of those used for transmit operations.
Ch.0 receive data: RXD0[7:0] (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1)
Ch.1 receive data: RXD1[7:0] (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6)
Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1)
Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6)
The receive data can be read out from this register.