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II CORE BLOCK: BCU (Bus Control Unit)
B-II-4-12 EPSON S1C33L03 FUNCTION PART
Output disable delay time
In cases when a device having a long output disable time is connected, if a read cycle for that device is
followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus
is not placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus
contention. This is accomplished by inserting a specified number of cycles between a read cycle and the next
bus operation. Care is required with the #CEx signals, however, since different areas may be asserted
consecutively. There are gaps between command signals such as #RD and #WRL/#WRH.
Check the specifications of the device to be connected before setting the output disable delay time.
The output disable delay time is inserted only in the following cases:
•when a read cycle from the external device that has had an output disable delay time set is followed by a
write cycle performed by the CPU; and
•when a read cycle from the external device that has had an output disable delay time set is followed by a
read cycle for a different area (including the internal device).
Conversely, no output disable delay time is inserted in the following conditions:
•immediately after a write cycle, and
•during a successive read from the same external device.
Setting Timing Conditions of Burst ROM
Wait cycles
If burst ROM is selected for area 10 or 9, the wait cycles to be inserted in the burst read cycle can be selected
in a range from 0 to 3 cycles. A10BW[1:0] (D[A:9]) / Areas 10–9 set-up register (0x48126) is used for this
selection. This selection is applied simultaneously to areas 10 and 9, so wait cycles can not be chosen
individually for each area. The wait cycles set at cold start is 0.
Even for a burst read, the SRAM settings of wait cycles in the first bus operation are valid. (Refer to
A10WT[2:0] in the foregoing section.)
The wait cycles set by A10BW[1:0] are inserted into the burst cycles after the first bus operation.
In addition, when burst ROM is selected, no wait cycles can be inserted into the read cycle via the #WAIT
pin.
For writing to an area that has had burst ROM selected, an SRAM write cycle is executed. In this case, both
the SRAM settings of wait cycles and those input via the #WAIT pin are valid.
Burst mode
The burst mode can be selected between an eight-consecutive-burst and a four-consecutive-burst mode.
RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is
selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At
cold start, the four-consecutive-burst mode is set by default.