Filter
Top Products
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-13
A-1
B-V
IDMA
Interrupt Function of Intelligent DMA
IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA
transfer itself.
Interrupt when invoked by an interrupt factor
If the corresponding bits of the IDMA request and interrupt enable registers are left set (= "1"), assertion of an
interrupt request is kept pending even when the enabled interrupt factor has occurred and the IDMA channel
assigned to that interrupt factor is invoked.
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is
completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At
the same time, the IDMA request register is cleared to "0". The IDMA enable bit is not cleared and remains
set to "1".
If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that
no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain
set to "1".
When DINTEN has been set to "0" (interrupt disabled), the interrupt factor flag is reset even if the transfer
counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the
IDMA enable bit is cleared.
When IDMA is invoked by the software trigger, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt
factor flag register (0x40281) will not be set.
For details about the interrupt factors that can be used to invoke IDMA and the interrupt control registers,
refer to the descriptions of the peripheral circuits in this manual.
Note that the priority levels of interrupt factors are set by the interrupt priority register. Refer to "ITC
(Interrupt Controller)". However, when compared between IDMA and interrupt requests, IDMA is given
higher priority over the other. Consequently, even when an interrupt factor occurring during an IDMA
transfer has higher priority than the interrupt factor that invoked the IDMA transfer, an interrupt request for it
or a new IDMA invocation request is not accepted until after the current IDMA transfer is completed.
Software-triggered interrupts
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer
operation is completed, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register
(0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = "0"
(interrupt disabled), the FIDMA flag is not set.
IDMA interrupt control register in the interrupt controller
The following registers are used to control an interrupt for the completion of IDMA transfer:
Interrupt factor flag: FIDMA (D4) / DMA interrupt factor flag register (0x40281)
Interrupt enable: EIDMA (D4) / DMA interrupt enable register (0x40271)
Interrupt level: PDM[2:0] (D[2:0]) / IDMA interrupt priority register (0x40265)
When a DMA transfer in the IDMA channel invoked by a trigger in the software application or subsequent
link is completed and the transfer counter is decremented to 0, the interrupt factor flag for the completion of
IDMA transfer is set to "1". However, this requires as a precondition that interrupt be enabled (DINTEN =
"1") in the control information for that channel. If the interrupt enable register bit remains set (= "1") when
the flag is set, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable
register bit cleared (= "0"). Use the interrupt priority register to set interrupt priority levels (0 to 7). An
interrupt request to the CPU is accepted on condition that no other interrupt request of higher priority is
generated.
Furthermore, it is only when the PSR's IE bit = "1" (interrupt enabled) and the set value of IL is smaller than
the IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA
interrupt request.
For details about these interrupt control registers, and for information on device operation when an interrupt
occurs, refer to "ITC (Interrupt Controller)".