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V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-3
A-1
B-V
HSDMA
Programming Control Information
The HSDMA operates according to the control information set in the registers.
Note that some control bits change their functions according to the address mode.
The following explains how to set the contents of control information. Before using HSDMA, make each the
settings described below.
Setting the Registers in Dual-Address Mode
Make sure that the HSDMA channel is disabled (HSx_EN = "0") before setting the control information.
Address mode
The address mode select bit DUALMx should be set to "1" (dual-address mode). This bit is set to "0" (single-
address mode) at initial reset.
DUALM0: Ch. 0 address mode selection (DF) / HSDMA Ch. 0 control register (0x48222)
DUALM1: Ch. 1 address mode selection (DF) / HSDMA Ch. 1 control register (0x48232)
DUALM2: Ch. 2 address mode selection (DF) / HSDMA Ch. 2 control register (0x48242)
DUALM3: Ch. 3 address mode selection (DF) / HSDMA Ch. 3 control register (0x48252)
Transfer mode
A transfer mode should be set using the DxMOD[1:0] bits.
D0MOD[1:0]:
Ch. 0 transfer mode (D[F:E]) / HSDMA Ch. 0 high-order destination address set-up register (0x4822A)
D1MOD[1:0]: Ch. 1 transfer mode (D[F:E]) / HSDMA Ch. 1 high-order destination address set-up register (0x4823A)
D2MOD[1:0]: Ch. 2 transfer mode (D[F:E]) / HSDMA Ch. 2 high-order destination address set-up register (0x4824A)
D3MOD[1:0]: Ch. 3 transfer mode (D[F:E]) / HSDMA Ch. 3 high-order destination address set-up register (0x4825A)
The following three transfer modes are available:
Single transfer mode (DxMOD = "00", default)
In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the
size set by DATSIZEx. If data transfer need to be performed a number of times as set by the transfer counter,
an equal number of triggers are required.
Successive transfer mode (DxMOD = "01")
In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer
counter. The transfer counter is decremented to 0 each time data is transferred.
Block transfer mode (DxMOD = "10")
In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of
the size set by BLKLENx. If a block transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
Transfer data size
The DATSIZEx bit is used to set the unit size of data to be transferred.
A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0"
(default).
DATSIZE0:
Ch. 0 transfer data size (DE) / HSDMA Ch. 0 high-order source address set-up register (0x48226)
DATSIZE1: Ch. 1 transfer data size (DE) / HSDMA Ch. 1 high-order source address set-up register (0x48236)
DATSIZE2: Ch. 2 transfer data size (DE) / HSDMA Ch. 2 high-order source address set-up register (0x48246)
DATSIZE3: Ch. 3 transfer data size (DE) / HSDMA Ch. 3 high-order source address set-up register (0x48256)