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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-31
A-1
B-VI
SDRAM
SDRSZ: SDRAM data path bit width (D6) / SDRAM advanced control register (0x39FFC9)
Select the SDRAM data-path bit width.
Write "1": 8 bits
Write "0": 16 bits
Read: Valid
Set SDRSZ to "1" to use an 8-bit SDRAM or to "0" to use a 16-bit SDRAM.
At cold start, SDRSZ is set to "0" (16 bits). At hot start, SDRSZ retains its status before being initialized.
SDRBI: SDRAM bank interleaved access (D5) / SDRAM advanced control register (0x39FFC9)
Enable the SDRAM's bank-interleaved access function.
Write "1": Interleaved
Write "0": One bank only
Read: Valid
Writing "1" to SDRBI activates multiple SDRAM banks at the same time, allowing for successive accesses of one
bank after another. If SDRBI = "0", multiple banks cannot be activated at the same time.
At cold start, SDRBI is set to "0" (one bank only). At hot start, SDRBI retains its status before being initialized.
SDRMRS: SDRAM mode register set flag (D7) / SDRAM status register (0x39FFCA)
Indicates the execution status of the MRS (Mode Register Set) command.
Read "1": Not finished
Read "0": Finished
Write: Invalid
SDRMRS is automatically set to "1" at power-on, and is reset to "0" by executing the MRS command in the
SDRAM initialization sequence. As the MRS command uses an external address bus, no other external devices can
be accessed until the command execution is finished. To access any external device other than the SDRAM
immediately after executing the SDRAM initialization sequence, read SDRMRS to confirm that the MRS
command execution is finished before attempting the intended access.
At cold start, SDRMRS is set to "1" (Not finished). At hot start, SDRMRS retains its status before being initialized.
SDRSRM: SDRAM current refresh mode (D6) / SDRAM status register (0x39FFCA)
Indicates the SDRAM refresh mode.
Read "1": Auto refresh mode
Read "0": Self refresh mode
Write: Invalid
SDRSRM is "0" while the SDRAM controller holds the SDCKE pin low (i.e., the SDRAM is in self-refresh mode).
Otherwise, SDRSRM = "1".
Before entering HALT2 or SLEEP mode or releasing the bus, always be sure to read this bit using a program stored
elsewhere (i.e., not in the SDRAM) to confirm that the SDRAM is in self-refresh mode.
At cold start, SDRSRM is set to "1" (auto refresh mode). At hot start, SDRSRM retains its status before being
initialized.