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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
B-VI-2-34 EPSON S1C33L03 FUNCTION PART
;;; SDRAM auto refresh count high-order register
xld.w %r0,0x39FFC7 ;
xld.w %r1,0x00 ;
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM self refresh count register
;;; xld.w %r0,0x39FFC8 ;
;;; xld.w %r1,0x0f ;
;;; ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM advanced control register
xld.w %r0,0x39FFC9 ;
xld.w %r1,0x20 ; data width -> 16bit, bank interleave -> on
ld.b [%r0],%r1 ;
;;;*****************************************************************
;;;***************** SDRAM controller power up *********************
;;;*****************************************************************
xld.w %r0,0x39FFC1 ; SDRAM control register
xld.w %r1,0x39FFCA ; SDRAM status register
xld.w %r2,0x0
xld.w %r3,0x10
;;; enable SDRAM signal
bset [%r0],0x7 ; set SDRENA[D7/0x39FFC1]
SDRAM_SIGNAL_EN:
add %r2,0x1 ; SDRAM signal enable waiting loop
cmp %r2,%r3
jrne SDRAM_SIGNAL_EN
;;; SDRAM power up
bset [%r0],0x6 ; set SDRINI[D6/0x39FFC1]
POWER_UP:
btst [%r1],0x7 ; SDRAM power-up waiting loop
jrne POWER_UP
;;;------------------------ end of SDRAM access configuration ---------------------------
ret
The SDRAM can be accessed after executing the above program.
Example of initialization routine for 4M words × 16 bits × 4 banks (32MB) of SDRAM
When using a 32MB SDRAM, modify two parts of the above program example indicated with (note 1) and (note
2) as follows:
(note 1)
;///////////////////////////////////////////
;;; SDRAM area configuration register
xld.w %r0,0x39FFC0 ;
xld.w %r1,0xc8 ; set area13&14 to SDRAM area, #SDCE0(#CE13) available
ld.b [%r0],%r1 ; (32MB area available)
;///////////////////////////////////////////
(note 2)
;///////////////////////////////////////////
;;; SDRAM address configuration register
xld.w %r0,0x39FFC2 ;
xld.w %r1,0x2a ; col 512 / row 8K / bank 4 -> 256Mb[32MB] available
ld.b [%r0],%r1 ;
;///////////////////////////////////////////