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APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-15
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040270
(B)
1 Enabled 0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B)
1 Enabled 0 Disabled
DMA interrupt
enable register
E16TC1
E16TU1
–
E16TC0
E16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040272
(B)
1 Enabled 0 Disabled
16-bit timer 0/1
interrupt
enable register
–
1 Enabled 0 Disabled
–
E16TC3
E16TU3
–
E16TC2
E16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040273
(B)
1 Enabled 0 Disabled
16-bit timer 2/3
interrupt
enable register
–
1 Enabled 0 Disabled
–
E16TC5
E16TU5
–
E16TC4
E16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040274
(B)
1 Enabled 0 Disabled
16-bit timer 4/5
interrupt
enable register
–
1 Enabled 0 Disabled
–
–
E8TU3
E8TU2
E8TU1
E8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.0040275
(B)
1 Enabled 0 Disabled
8-bit timer
interrupt
enable register
–
ESTX1
ESRX1
ESERR1
ESTX0
ESRX0
ESERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040276
(B)
1 Enabled 0 Disabled
Serial I/F
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B)
1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register