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APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-37
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC1_L7
TC1_L6
TC1_L5
TC1_L4
TC1_L3
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
BLKLEN16
BLKLEN15
BLKLEN14
BLKLEN13
BLKLEN12
BLKLEN11
BLKLEN10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer c
ounter[7:0]
(block transfer mode)
Ch.1 transfer counter[15:8]
(single/successive transfer mode)
Ch.1 block length
(block transfer mode)
Ch.1 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048230
(HW)
High-speed
DMA Ch.1
transfer
counter
register
–
–
DUALM1
D1DIR
–
TC1_H7
TC1_H6
TC1_H5
TC1_H4
TC1_H3
TC1_H2
TC1_H1
TC1_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 address mode selection
D) Invalid
S) Ch.1 transfer direction control
reserved
Ch.1 transfer counter[15:8]
(block transfer mode)
Ch.1 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048232
(HW)
High-speed
DMA Ch.1
control register
Note:
D) Dual address
mode
S) Single
address
mode
S1ADRL15
S1ADRL14
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 source address[15:0]
S) Ch.1 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048234
(HW)
High-speed
DMA Ch.1
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE1
S1IN1
S1IN0
S1ADRH11
S1ADRH10
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.1 transfer data size
D) Ch.1 source address control
S) Ch.1 memory address control
D) Ch.1 source address[27:16]
S) Ch.1 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048236
(HW)
1 Half word 0 Byte
High-speed
DMA Ch.1
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–