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V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-16 EPSON S1C33L03 FUNCTION PART
Intelligent DMA
Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of
HSDMA. The following shows the IDMA channels set in HSDMA:
IDMA channel
Channel 0 end-of-transfer interrupt: 0x05
Channel 1 end-of-transfer interrupt: 0x06
Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must
be set to "1". Settings of transfer conditions on the IDMA side are also required.
Table 2.4 Control Bits for IDMA Transfer
Channel IDMA request bit IDMA enable bit
Ch. 0 RHDM0(D4/0x40290) DEHDM0(D4/0x40294)
Ch. 1 RHDM1(D5/0x40290) DEHDM1(D5/0x40294)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
Trap vector
The trap vector addresses for interrupt factors in each channel are set by default as follows:
Channel 0 end-of-transfer interrupt: 0x0C00058
Channel 1 end-of-transfer interrupt: 0x0C0005C
Channel 2 end-of-transfer interrupt: 0x0C00060
Channel 3 end-of-transfer interrupt: 0x0C00064
Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137).