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S1C33L03 PRODUCT PART EPSON A-9
A-1
Pin name Pin No. I/O Pull-up Function
P11
EXCL1
T8UF1
DST1
121 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1",
IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DST1:DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)
P12
EXCL2
T8UF2
DST2
120 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1",
IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"
T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6)
= "1" and CFEX0(D0/0x402DF) = "0"
DST2:DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)
P13
EXCL3
T8UF3
DPCO
119 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1",
IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DPCO:DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)
P14
FOSC1
DCLK
118 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and
CFEX0(D0/0x402DF) = "0"
DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)
P15
EXCL4
#DMAEND0
#SCLK3
LDQM
84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",
IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4)
= "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"
#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",
CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
LDQM: SDRAM data (low byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P16
EXCL5
#DMAEND1
SOUT3
83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and
IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) =
"1" and IOC16(D6/0x402D6) = "1"
SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and
CFP16(D6/0x402D4) = "0"
P20
#DRD
SDCKE
80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DRD: DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"
SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"
P21
#DWE
#GAAS
#SDWE
79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0" (default)
#DWE: DRAM write signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0"
#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"
P22
TM0
1 I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)
TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"
P23
TM1
2 I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)
TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"
P24
TM2
#SRDY2
4 I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)
TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1"
#SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1"
and CFP24(D4/0x402D8) = "0"
P25
TM3
#SCLK2
5 I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)
TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1"
#SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and
CFP25(D5/0x402D8) = "0"