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APPENDIX: I/O MAP
B-APPENDIX-42 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D3ADRL15
D3ADRL14
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048258
(HW)
High-speed
DMA Ch.3
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D3MOD1
D3MOD0
D3IN1
D3IN0
D3ADRH11
D3ADRH10
D3ADRH9
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer mode
D) Ch.3 destination address
control
S) Invalid
D) Ch.3 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004825A
(HW)
High-speed
DMA Ch.3
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D3MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS3_EN
DF–1
D0
reserved
Ch.3 enable
1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004825C
(HW)
High-speed
DMA Ch.3
enable register
––
HS3_TF
DF–1
D0
reserved
Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading)
1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004825E
(HW)
High-speed
DMA Ch.3
trigger flag
register