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III PERIPHERAL BLOCK: SERIAL INTERFACE
B-III-8-38 EPSON S1C33L03 FUNCTION PART
EPR0: Ch.0 parity enable (D5) / Serial I/F Ch.0 control register (0x401E3)
EPR1: Ch.1 parity enable (D5) / Serial I/F Ch.1 control register (0x401E8)
EPR2: Ch.2 parity enable (D5) / Serial I/F Ch.2 control register (0x401F3)
EPR3: Ch.3 parity enable (D5) / Serial I/F Ch.3 control register (0x401F8)
Selects a parity function.
Write "1": Parity added
Write "0": No parity added
Read: Valid
EPRx is used to select whether receive data is to be checked for parity, and whether a parity bit is to be added to
transmit data. When EPRx is set to "1", the receive data is checked for parity. A parity bit is automatically added to
the transmit data. When EPRx is set to "0", parity is not checked and no parity bit is added.
The parity function is only valid in the asynchronous mode. Settings of EPRx have no effect in the clock-
synchronized mode.
At initial reset, EPRx becomes indeterminate.
PMD0: Ch.0 parity mode selection (D4) / Serial I/F Ch.0 control register (0x401E3)
PMD1: Ch.1 parity mode selection (D4) / Serial I/F Ch.1 control register (0x401E8)
PMD2: Ch.2 parity mode selection (D4) / Serial I/F Ch.2 control register (0x401F3)
PMD3: Ch.3 parity mode selection (D4) / Serial I/F Ch.3 control register (0x401F8)
Selects an odd or even parity.
Write "1": Odd parity
Write "0": Even parity
Read: Valid
Odd parity is selected by writing "1" to PMDx, and even parity is selected by writing "0". Parity check and the
addition of a parity bit are only effective in asynchronous transfers in which EPRx is set to "1". If EPRx = "0",
settings of PMDx do not have any effect.
At initial reset, PMDx becomes indeterminate.
STPB0: Ch.0 stop bit selection (D3) / Serial I/F Ch.0 control register (0x401E3)
STPB1: Ch.1 stop bit selection (D3) / Serial I/F Ch.1 control register (0x401E8)
STPB2: Ch.2 stop bit selection (D3) / Serial I/F Ch.2 control register (0x401F3)
STPB3: Ch.3 stop bit selection (D3) / Serial I/F Ch.3 control register (0x401F8)
Selects a stop-bit length during the performance of an asynchronous transfer.
Write "1": 2 bits
Write "0": 1 bit
Read: Valid
STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop
bit is selected by writing "0". The start bit is fixed at 1 bit.
Settings of STPBx are ignored during the performance of a clock-synchronized transfer.
At initial reset, STPBx becomes indeterminate.