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III PERIPHERAL BLOCK: PRESCALER
B-III-2-6 EPSON S1C33L03 FUNCTION PART
CLGP7–CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)
These bits remove the protection against writing to addresses 0x40180 and 0x40190.
Write "0b10010110": Write protection removed
Write other than the above: No operation (write-protected)
Read: Valid
Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against
writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to
"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.
At initial reset, CLGP is set to "0b00000000" (write-protected).
PSCDT0: Prescaler clock selection (D0) / Prescaler clock select register (0x40181)
Select the source clock for the prescaler.
Write "1": OSC1 clock
Write "0": OSC3 clock/PLL output clock
Read: Valid
When "1" is written to PSCDT0, the OSC1 clock (typ. 32 kHz) is selected.
When "0" is written, the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is
selected.
For the prescaler clock, the clock source same as the CPU operating clock must be selected.
At initial reset, PSCDT0 is set to "0" (OSC3 clock/PLL output clock).
P16TS0[2:0]:16-bit timer 0 clock division ratio (D[2:0]) / 16-bit timer 0 clock control register (0x40147)
P16TS1[2:0]:16-bit timer 1 clock division ratio (D[2:0]) / 16-bit timer 1 clock control register (0x40148)
P16TS2[2:0]:16-bit timer 2 clock division ratio (D[2:0]) / 16-bit timer 2 clock control register (0x40149)
P16TS3[2:0]:16-bit timer 3 clock division ratio (D[2:0]) / 16-bit timer 3 clock control register (0x4014A)
P16TS4[2:0]:16-bit timer 4 clock division ratio (D[2:0]) / 16-bit timer 4 clock control register (0x4014B)
P16TS5[2:0]:16-bit timer 5 clock division ratio (D[2:0]) / 16-bit timer 5 clock control register (0x4014C)
P8TS0[2:0]:8-bit timer 0 clock division ratio (D[2:0]) / 8-bit timer 0/1 clock control register (0x4014D)
P8TS1[2:0]:8-bit timer 1 clock division ratio (D[6:4]) / 8-bit timer 0/1 clock control register (0x4014D)
P8TS2[2:0]:8-bit timer 2 clock division ratio (D[2:0]) / 8-bit timer 2/3 clock control register (0x4014E)
P8TS3[2:0]:8-bit timer 3 clock division ratio (D[6:4]) / 8-bit timer 2/3 clock control register (0x4014E)
P8TS4[2:0]:8-bit timer 4 clock division ratio (D[2:0]) / 8-bit timer 4/5 clock control register (0x40145)
P8TS5[2:0]:8-bit timer 5 clock division ratio (D[6:4]) / 8-bit timer 4/5 clock control register (0x40145)
PSAD[2:0]:A/D converter clock division ratio (D[2:0]) / A/D clock control register (0x4014F)
Select a clock for each peripheral circuit.
The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division
ratio differs for each peripheral circuit.
These bits can also be read out.
At initial reset, all of these bits are set to "0b000" (highest frequency available).