Filter
Top Products
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-17
A-1
B-V
IDMA
Programming Notes
(1) Before setting the IDMA base address, be sure to disable DMA transfers (IDMAEN = "0"). Writing to the
IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the
register is read during a DMA transfer, the data is indeterminate. When setting or rewriting control
information for each channel, make sure that DMA transfers will not occur in any channel.
(2) The address that is set in the IDMA base address register must always be a word (32-bit) boundary address.
(3) After an initial reset, the interrupt factor flag (FIDMA) becomes indeterminate. To prevent unwanted
interrupts from occurring, be sure to reset the flag in a program.
(4) Once an interrupt occurs, be sure to reset the interrupt factor flag (FIDMA) before setting up the PSR again or
executing the reti instruction. This ensures that an interrupt will not be generated for the same factor.
(5) If all the following conditions are met, the transfer counter value becomes invalid during IDMA transfer so
data cannot be transferred properly.
1. The IDMA control information (source/destination addresses, transfer counter, etc.) is placed in the
external EDO DRAM.
2. The DRAM access timing condition is set to EDO mode by the BCU register.
3. The bus clock is set to x2 speed mode (#X2SPD pin = "0").
When placing the control information in the EDO DRAM in x2 speed mode, the DRAM access timing
condition must be set to high-speed page mode.
Or place the control information in the internal RAM. Using the internal RAM increases the performance
because the overhead during IDMA transfer is decreased to 6 cycles on both load/store operations.
(6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a setting of 0 in clock option register HLT2OP (D3/0x40190), that operation will be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.