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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-29
A-1
B-VI
SDRAM
SDRBA: Number of SDRAM banks (D1) / SDRAM address configuration register (0x39FFC2)
Set the number of banks of the SDRAM.
Write "1": 4 banks
Write "0": 2 banks
Read: Valid
Set "1" when a SDRAM configured with 4 banks is used or set "0" when a SDRAM configured with 2 banks is
used.
The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM.
At cold start, SDRBA is set to "0" (2 banks). At hot start, SDRBA retains its status before being initialized.
SDRCL1–SDRCL0: SDRAM CAS latency (D[6:5]) / SDRAM mode set-up register (0x39FFC3)
Set the CAS latency of the SDRAM.
Table 2.17 Setting CAS Latency
SDRCL1 SDRCL0 CAS latency (number of clocks)
10 2
Other settings Not allowed
The SDRAM controller does not support CAS latencies other than 2.
At cold start, SDRCL is set to "11". Be sure to reset to "10" so that the CAS latency is set to 2. At hot start, SDRCL
retain its status before being initialized.
SDRBL1–SDRBL0: SDRAM burst length (D[3:2]) / SDRAM mode set-up register (0x39FFC3)
Set the burst read length of the SDRAM.
Table 2.18 Setting Burst Length
SDRBL1 SDRBL0 Burst length (word)
00 1
01 2
10 4
11 8
The SDRAM controller does not support burst write, so the set burst length is effective only for read cycles.
At cold start, SDRBL is set to "11" (8). At hot start, SDRBL retain its status before being initialized.
SDRTRAS2–SDRTRAS0: SDRAM t
RAS spec (D[7:5]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRAS SDRAM parameter (ACTIVE to PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–7 sets the period to 1–7 clock cycles. Specifying 0 sets the period to 8 clock cycles.
At cold start, SDRTRAS is set to "000" (8). At hot start, SDRTRAS retain its status before being initialized.
SDRTRP1–SDRTRP0: SDRAM t
RP spec (D[4:3]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRP SDRAM parameter (PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles.
At cold start, SDRTRP is set to "00" (4). At hot start, SDRTRP retain its status before being initialized.
SDRTRC2–SDRTRC0: SDRAM t
RC spec (D[2:0]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRC SDRAM parameter (ACTIVE to ACTIVE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–7 sets the period to 1–7 clock cycles. Specifying 0 sets the period to 8 clock cycles.
At cold start, SDRTRC is set to "000" (8). At hot start, SDRTRC retain its status before being initialized.
Note:When the auto-refresh command is executed, the following command may be issued 3 or 4
CPU_CLK cycles from that point regardless of the t
RC value set in the SDRTRC register.
Therefore, use SDRAMs with 75 ns or less of t
RC.