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V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-22 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
S1ADRL15
S1ADRL14
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 source address[15:0]
S) Ch.1 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048234
(HW)
High-speed
DMA Ch.1
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE1
S1IN1
S1IN0
S1ADRH11
S1ADRH10
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.1 transfer data size
D) Ch.1 source address control
S) Ch.1 memory address control
D) Ch.1 source address[27:16]
S) Ch.1 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048236
(HW)
1 Half word 0 Byte
High-speed
DMA Ch.1
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D1ADRL15
D1ADRL14
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048238
(HW)
High-speed
DMA Ch.1
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode