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III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-23
A-1
B-III
I/O
FP3–FP0: Port input 3–0 interrupt factor flag (D[3:0]) /
Key input, port input 0–3 interrupt factor flag register (0x40280)
FP7–FP4: Port input 7–4 interrupt factor flag (D[5:2]) /
Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
FK1, FK0: Key input 1, 0 interrupt factor flag (D[5:4]) /
Key input, port input 0–3 interrupt factor flag register (0x40280)
Indicates the status of an input interrupt factor generated.
When read
Read "1": Interrupt factor has occurred
Read "0": No interrupt factor has occurred
When written using the reset-only method (default)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
FP and FK are an interrupt factor flags corresponding to the port-input interrupt and the key-input interrupt,
respectively. The flag is set to "1" when interrupt generation conditions are met.
At this time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher priority has been generated.
3. The IE bit of the PSR is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.
When using the interrupt factor of the port-input to request IDMA, note that even when the above conditions are
met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled
at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is
completed.
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
interrupt enable and interrupt priority registers are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used.
At initial reset, all the flags become indeterminate, so be sure to reset them in the software.