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III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-8 EPSON S1C33L03 FUNCTION PART
8-Bit Programmable Timer Interrupts and DMA
The 8-bit programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to
3.
The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section.
Control registers of the interrupt controller
Table 3.3 shows the interrupt controller's control register provided for each timer.
Table 3.3 Control Registers of Interrupt Controller
Timer Interrupt factor flag Interrupt enable register Interrupt priority register
Timer 0 F8TU0(D0/0x40285) E8TU0(D0/0x40275) P8TM[2:0](D[2:0]/0x40269)
Timer 1 F8TU1(D1/0x40285) E8TU1(D1/0x40275)
Timer 2 F8TU2(D2/0x40285) E8TU2(D2/0x40275)
Timer 3 F8TU3(D3/0x40285) E8TU3(D3/0x40275)
When the timer underflows, the corresponding interrupt factor flag is set to "1". If the interrupt enable register
bit corresponding to that interrupt factor flag has been set to "1", an interrupt request is generated.
An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to
"0". The interrupt factor flag is set to "1" whenever the timer underflows, regardless of how the interrupt
enable register is set (even when it is set to "0").
The interrupt priority register sets an interrupt priority level (0 to 7) for the four timers as one interrupt source.
Within 8-bit programmable timers, timer 0 has the highest priority and timer 3 the lowest. An interrupt
request to the CPU is accepted on the condition that no other interrupt request of a higher priority has been
generated.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer
interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the
CPU.
For details on these interrupt control registers and device operation when an interrupt has occurred, refer to
"ITC (Interrupt Controller)".
Intelligent DMA
The underflow interrupt factor of the timer 0 to 3 can invoke intelligent DMA (IDMA). This enables
memory-to-memory DMA transfers to be performed cyclically.
The following shows the IDMA channel numbers set to each timer:
IDMA channel
Timer 0: 0x13
Timer 1: 0x14
Timer 2: 0x15
Timer 3: 0x16
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 3.4 must be set to "1" in
advance. Transfer conditions, etc. must also be set on the IDMA side in advance.
Table 3.4 Control Bits for IDMA Transfer
Timer IDMA request bitIDMA enable bit
Timer 0 R8TU0(D2/0x40292) DE8TU0(D2/0x40296)
Timer 1 R8TU1(D3/0x40292) DE8TU1(D3/0x40296)
Timer 2 R8TU2(D4/0x40292) DE8TU2(D4/0x40296)
Timer 3 R8TU3(D5/0x40292) DE8TU3(D5/0x40296)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".