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III PERIPHERAL BLOCK: SERIAL INTERFACE
B-III-8-34 EPSON S1C33L03 FUNCTION PART
SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB)
Switches the function of pin P25/TM3/#SCLK2.
Write "1": #SCLK2
Write "0": P25/TM3
Read: Valid
To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1" and CFP25 (D5 / 0x402D8) to "0".
To use the pin as P25 or TM3, set this bit to "0".
At power-on, this bit is set to "0".
SSRDY2: Serial I/F Ch.2 SRDY selection (D3) / Port SIO function extension register (0x402DB)
Switches the function of pin P24/TM2/#SRDY2.
Write "1": #SRDY2
Write "0": P24/TM2
Read: Valid
To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0".
To use the pin as P24 or TM2, set this bit to "0".
At power-on, this bit is set to "0".
CFEX7–CFEX4: P0[7:4] pin function selection (D[7:4]) / Port function extension register (0x402DF)
Selects the extended function of pins P07–P04.
Write "1": Function-extended pin
Write "0": I/O-port/serial I/O pin
Read: Valid
When CFEX[7:4] is set to "1", the P07–P04 ports function as DMA signal output ports. When CFEX[7:4] = "0",
the CFP0[7:4] bit becomes effective, so the settings of these bits determine whether the P07–P04 ports function as
I/O port s or serial interface Ch.1 signal output ports.
At cold start, CFEX[7:4] is set to "0" (I/O-port/serial I/O pin). At hot start, CFEX[7:4] retains its state from prior to
the initial reset.
TXD07–TXD00: Ch.0 transmit data (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
TXD17–TXD10: Ch.1 transmit data (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
TXD27–TXD20: Ch.2 transmit data (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
TXD37–TXD30: Ch.3 transmit data (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
Sets transmit data.
When data is written to this register (transmit buffer) after "1" is written to TXENx, a transmit operation is begun.
TDBEx is set to "1" (transmit-buffer empty) when the data is transferred to the shift register. A transmit-buffer
empty interrupt factor is simultaneously generated. The next transmit data can be written to the buffer at any time
thereafter, even when the serial interface is sending data.
In the 7-bit asynchronous mode, TXDx7 (MSB) is ignored.
The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are
output as high-level signals and those set to "0" output as low-level signals.
This register can be read as well as written.
At initial reset, the content of TXDx becomes indeterminate.